Digital message synchronization is a process whereby expected data is aligned with received data, thereby allowing synchronization of the received digital data at a data receiver. Conventional methods for determining byte or message alignment within a digital stream of data generally require very high levels of computation power, even for relatively low bit rate data streams. Known systems provide a synchronization detector that is generally realized using discrete hardware, or achieved using a high-speed processor having specialized features, such as, for example a digital signal processor (DSP) or dedicated circuitry in an application-specific integrated circuit (ASIC), or the like.
Using current methods for aligning data can add significant cost and complexity to microprocessor based systems. For example, in known systems, the microprocessor typically consumes large amounts of its computation ability and resources performing, or attempting to perform, rapid real-time shifts and real-time comparisons of the data stream to find a framing pattern or unique word in the received bit stream. The framing pattern is generally contained in the data stream and does not have any known byte boundaries.
General purpose microprocessors are not well suited to performing shifting and masking of relatively long bit streams which are generally required for the detection of sync patterns, i.e., unique words in serial data streams. These problems are further exacerbated when control messages or sync patterns are embedded into a data stream in a relatively asynchronous manner. Conventional methods require the synchronization detector to compare the incoming bit stream to the sync pattern on a bit-by-bit basis, and requires the capability to remember and reexamine the received bits even when only a partial match, generally referred to as a false start, is found. Accordingly, conventional message synchronization systems are inherently inefficient and require a great deal of memory and processing power.